A binary adder having multiple, 1024 to 2048, bits must be operated at high speed in order to process RSA encryption rapidly. However, according to a conventional technique, to be described below, the speed at which a binary adder can be operated is limited by a carry signal transmitted from a lower level, and a desirable operating speed can not be acquired. The conventional technique will now be described.
(1) Ripple carry system
A ripple adder comprises parallel arranged full adders whose number is equivalent to that of the bits. But while a circuit required for a ripple carry system is not complicated, the maximum gate delay is equivalent to the total of the gate delays of the bits involved, and it is therefore very difficult to ensure a desirable operating speed.
(2) Carry monitoring system
Since the maximum gate delay of the ripple adder is the maximum N stages for N bits, an ensured operating speed is reduced in inverse proportion to the number of bits. However, since the transfer of a carry is required only when two values, X and Y, to be added together are exclusively 1 and when a carry is transmitted from a lower level, these conditions are rarely sequential. For 1024 bits, as it is calculated that the above conditions happen for at most 11 sequential bits, the average operating speed is anticipated to be 100 times the ensured operating speed. In this system, a carry monitoring circuit is additionally provided to enter a waiting time when carries occur continuously. The carry monitoring system, however, requires a large circuit, and will increase power consumption and potentially will destabilize the operation.
(3) Carry skip system
A binary adder is divided into several blocks to perform the addition in individual blocks, and a+1 compensation by a carry signal from a lower level. A binary adder according to this system is called a carry skip adder. Although it has a complicated circuit, the carry skip system requires only a small amount of power, and its operation is stable. The circuit for this system is more complicated than the ripple adder, and is as complicated as the adder for the carry monitor system.
In a one-stage carry step system, for the addition of N bits, n such that N.ltoreq.n(n+2)/2+2 is acquired and (n+3) is a gate delay for n. For 1024 bits, N 1024 and n=45, i.e., a gate delay of 48 is obtained.
The carry skip system is described in, for example, Information Processing, Vol. 37, No. 1 pp. 80-85, Information Processing Institute, January 1996.
Furthermore, two-stage carry skip adder is described in IBM Technical Disclosure Bulletin Vol. 27, No. 11, April 1985, pp. 6785-6787. Since a binary adder is divided into blocks symmetrically, the operating speed is high for a small number of bits, but as the effect of skipping carries is reduced when handling a lot of bits, the operating speed becomes relatively slower.